Memory Map

The PIC18F46J11 has 3,776 bytes of RAM organized into banks, plus 1KB of internal EEPROM for persistent storage. This page documents the key memory locations used by the RS-UV3 firmware.

RAM Organization

Serial Communication

Address	Name	Description
`0x059a`	`cmd_char0`	Serial buffer pointer (low byte)
`0x059b`	`cmd_char1`	Serial buffer pointer (high byte)
`0x059d`	`port_selector`	Which port received command: 1=USB, 2=DE-9
`0x059f`	`cmd_param`	Parsed numeric parameter
`0x05a0`	`response_port`	Output port for response
`0x05df`	`output_port`	Current serial output destination

String Table Interface

Address	Name	Description
`0x05e0`	`str_tbl_lo`	String table index (low byte)
`0x05e1`	`str_tbl_hi`	String table index (high byte)
`0x05e2`	`str_length`	String length for transmission

Frequency Storage

Address	Name	Description
`0x045d–0x0460`	`freq_main`	Main frequency (4 bytes, kHz × 100)
`0x0459–0x045c`	`freq_sub`	Sub/offset frequency (4 bytes)
`0x0461–0x0464`	`freq_tx`	TX frequency when split
`0x0467`	`power_level`	TX power: 0=low, 1=high

Configuration Flags

Address	Name	Description
`0x0423`	`io_config`	AI/AO analog I/O configuration
`0x0425`	`config_flags`	Audio filter, power, misc flags
`0x0454`	`squelch_mode`	Squelch sensitivity: L/M/H
`0x046a`	`tone_mode`	CTCSS mode: 0=off, 1=encode, 2=enc+dec

Math Library Workspace

The firmware implements 32-bit multiply and divide using shift-and-add. These addresses are the working registers:

Address	Name	Description
`0x0000–0x0003`	`Common_RAM`	32-bit accumulator (bank 0)
`0x05a1–0x05a4`	`math_op_a`	First operand
`0x05a5–0x05a8`	`math_op_b`	Second operand
`0x05a9–0x05ac`	`math_result`	Result storage

I2C Communication

Address	Name	Description
`0x05e3`	`i2c_addr`	Target I2C address
`0x05e4`	`i2c_data`	Data byte for transfer
`0x05e5`	`i2c_status`	Transfer status/error code

EEPROM Layout

The PIC18F46J11 has 1KB of internal EEPROM. The RS-UV3 uses it for persistent configuration:

Channel Memories (0x00–0x5F)

Each channel uses 10 bytes:

Offset	Size	Content
+0	4	RX frequency (kHz × 100)
+4	4	TX frequency (kHz × 100)
+8	1	CTCSS tone index
+9	1	Flags (power, squelch mode)

Channels 1–9 are stored at 0x00, 0x0A, 0x14, etc. Channel 0 is the power-on default configuration.

System Configuration (0x5A–0x6F)

Address	Content
`0x5A`	Squelch level (0–9)
`0x5B`	Squelch sensitivity
`0x5C`	Volume level (0–39)
`0x5D`	Audio filter flags
`0x5E–0x5F`	Beacon timer (seconds)
`0x60–0x63`	Reserved
`0x64`	Bandwidth setting
`0x65`	VOX sensitivity
`0x66`	Hang time (×10 ms)
`0x67`	COR inhibit time

Beacon Message (0x70–0x8F)

32 bytes for the beacon message text (null-terminated ASCII).

Callsign (0x90–0xA3)

20 bytes for the station callsign (null-terminated ASCII).

Special Function Registers

Key PIC18F46J11 SFRs used by the firmware:

UART (Serial)

Register	Address	Purpose
`TXSTA1`	`0xFAC`	UART1 transmit status
`RCSTA1`	`0xFAB`	UART1 receive status
`TXREG1`	`0xFAD`	UART1 transmit data
`RCREG1`	`0xFAE`	UART1 receive data
`SPBRG1`	`0xFAF`	UART1 baud rate generator
`TXSTA2`	`0xF6C`	UART2 transmit status
`RCSTA2`	`0xF6B`	UART2 receive status

I2C (MSSP)

Register	Address	Purpose
`SSPCON1`	`0xFC6`	MSSP control 1
`SSPCON2`	`0xFC5`	MSSP control 2
`SSPSTAT`	`0xFC7`	MSSP status
`SSPBUF`	`0xFC9`	MSSP data buffer
`SSPADD`	`0xFC8`	I2C address/baud

ADC

Register	Address	Purpose
`ADCON0`	`0xFC2`	ADC control 0
`ADCON1`	`0xFC1`	ADC control 1
`ADRESH`	`0xFC4`	ADC result high
`ADRESL`	`0xFC3`	ADC result low

Interrupts

Register	Address	Purpose
`INTCON`	`0xFF2`	Interrupt control
`PIR1`	`0xF9E`	Peripheral interrupt flags 1
`PIE1`	`0xF9D`	Peripheral interrupt enable 1

Memory Access Patterns

Reading from String Table

The firmware stores response strings in program memory. To send a string:

movlw   0x74                ; String index low
movwf   str_tbl_lo
movlw   0x00                ; String index high
movwf   str_tbl_hi
call    serial_send_string  ; Sends until null terminator

EEPROM Read

movlw   0x5A                ; EEPROM address
movwf   EEADR
bcf     EECON1, EEPGD       ; Select data EEPROM
bcf     EECON1, CFGS        ; Not configuration
bsf     EECON1, RD          ; Start read
movf    EEDATA, W           ; Read result

EEPROM Write

movlw   0x5A                ; Address
movwf   EEADR
movlw   0x05                ; Data to write
movwf   EEDATA
bcf     EECON1, EEPGD
bcf     EECON1, CFGS
bsf     EECON1, WREN        ; Enable writes
; Required unlock sequence
movlw   0x55
movwf   EECON2
movlw   0xAA
movwf   EECON2
bsf     EECON1, WR          ; Start write
; Wait for completion
btfsc   EECON1, WR
bra     $-2
bcf     EECON1, WREN        ; Disable writes

The unlock sequence (0x55, 0xAA) is a hardware requirement to prevent accidental writes.